1. Field of the Invention
The present invention relates to sequential access memories, and more particularly, to a sequential access memory including an address pointer for providing a row or column select signal to access an internal memory cell.
2. Description of the Background Art
Signal processing techniques, particularly techniques of image and video signal processing widely used in TV receivers, facsimile devices, and copiers have become important these recent years. The trend of this signal processing is towards digital technology superior in accuracy and reliability from the conventional analog technology according to progress in the semiconductor technology. This field has evolved tremendously these few years.
In signal processing using digital technology, a semiconductor memory is required that temporarily stores a signal which is to be delayed. For data representing one image or picture, data corresponding to each pixel forming that picture is sequentially transferred to be processed from one corner of the screen. A sequential access memory (referred to as SAM hereinafter) is generally used as a semiconductor memory employed for delaying data.
A conventional SAM will be described hereinafter with reference to FIG. 30 showing the main components thereof.
Referring to FIG. 30, a memory access array MA includes a plurality of memory circuits MC arranged in n rows and m columns. Each memory circuit MC holds k bits of data. A plurality of row select lines Qr1-Qrn are provided corresponding to the plurality of rows in memory cell array MA. Also, a plurality of column select lines Qc1-Qcm are provided corresponding to the plurality of columns in memory cell array MA.
A row address pointer RA applies sequential row select signals Qr1-Qrn (in the following, signal lines and signals transmitted to that signal line are denoted with the same reference character) are provided to the plurality of row select lines Qr1-Qrn to sequentially select one row out of memory cell array MA. Row address pointer RA includes a plurality of registers R for sequentially shifting data (row select signal) in synchronization with an input clock signal, and an even number of NOT logic circuits IR for feeding back an output signal of register R of the last stage to register R of the first stage. NOT logic circuit IR serves as a buffer for driving the wiring capacity.
Column address pointer CA provides sequential column select signals Qc1-Qcm to the plurality of column select lines Qc1-Qcm to sequentially select one row from memory cell array MA. Similar to row address pointer RA, column address pointer CA includes a plurality of registers R for sequentially shifting data (column select signal) in synchronization with an input clock signal, and an even number of NOT logic circuits IC for feeding back an output signal of register R of the last stage to register R of the first stage. NOT logic circuit IC serves as a buffer for driving the wiring capacity.
The operation of an SAM having the above structure will be described hereinafter with reference to the timing chart of FIG. 31.
Referring to FIG. 31, in the first cycle, the plurality of registers R in row address pointer RA respond to a clock signal to sequentially shift data of an H level (logical high). As a result, row select signals Qr1-Qrn sequentially attain an H level, whereby m rows in memory cell array MA are sequentially selected. In the first cycle, column select signal Qc1 is maintained at an H level by column address pointer CA. As a result, memory circuit MC of the first row of the first column, memory circuit MC of the second row of the first column, . . . , memory circuit MC of the n-th row of the first column are sequentially selected. Data is written into or read out from the selected memory circuit.
The data of an H level held in register R of the last stage in row address pointer RA is shifted to register R of the first stage via NOT logic circuit IR. Therefore, at the second cycle, the plurality of registers R in row address pointer RA respond to a clock signal to sequentially shift the data of an H level, whereby row select signals Qr1-Qrn are sequentially rendered to an H level. In the second cycle, column select signal Qc2 is held at an H level by column address pointer CA. Therefore, the second column of memory cell array MA is selected. As a result, memory circuit MC of the first row of the second column, memory circuit MC of the second row of the second column, . . . , memory circuit MC of the n-th row of the second column are sequentially selected.
Similarly, at the m-th cycle, memory circuit MC of the first row of the m-th column, memory circuit MC of the second row of the n-th column, . . . , memory circuit MC of the m-th row of the m-th column are sequentially selected. Data of an H level held in register R of the last stage in column address pointer CA is shifted to register R of the first stage via NOT logic circuit IC. As a result, following the selection of memory circuit MC of the n-th row of the m-th column in memory array MA, memory circuit MC of the first row of the first column is selected. Then, the first to m-th cycles are sequentially repeated.
An example of a register in the row and column address pointers shown in FIG. 30 will be described hereinafter with reference to the circuit diagram of FIG. 32.
Referring to FIG. 32, a register includes p channel MOS transistors Q101-Q104, n channel MOS transistors Q105-Q108, and NOT logic circuits G201-G204. Transistors Q101 and Q105 form a CMOS transmission gate. Similarly, transistors Q102-Q104 and corresponding transistors Q106-Q108 respectively form a CMOS transmission gate. A clock signal CLKA is provided to transistors Q105, Q102, Q103, and Q108. A clock signal CLKB is applied to transistors Q101, Q106, Q107, and Q104. FIG. 33 is a timing chart showing a clock signal provided to the register of FIG. 32. As shown in FIG. 33, clock signals CLKA and CLKB form a two layered clock wherein the period of the H levels do not overlap each other.
Transistors Q101 and Q105 receive a signal Xj output from the register of a preceding stage. A signal Xj+1 which is to be provided to the register of the next stage is output from a node (N3) of NOT logic circuit G204 and transistors Q104 and Q108. Signal Xj+1 is provided to memory cell array MA as a row or column select signal Q.
When clock signal CLKA attains an L level (logical low) and clock signal CLKB attains an H level, transistors Q102 and Q106, and transistors Q103 and Q107 are turned on, and transistors Q101 and Q105, and transistors Q104 and Q108 are turned off. Therefore, the signal applied to node N2 is latched by a latch circuit formed of NOT logic circuits G201, G202 and transistors Q102, Q106, and also output to node N3 as signal Xj+1 via transistors Q103, Q107 and NOT logic circuits G203, G204.
When clock signal CLKA attains an H level and clock signal CLKB attains an L level, transistors Q101, Q105, and transistors Q104, Q108 are turned on, and transistors Q103, Q107, and transistors Q102, Q106 are turned off. Therefore, signal Xj applied to node N1 is provided to node N2 via transistors Q101, Q105 and NOT logic circuits G201, G202. Also, signal Xj+1 of node N3 is latched by a latch circuit formed of NOT logic circuits G203, G204 and transistors Q104 and Q108. As a result, signal Xj applied to node N1 is shifted to node N3 in response to clock signals CLKA and CLKB.
In FIG. 33, it is assumed that the time period in which clock signal CLKA attains an L level and an H level only once is one period T. As to a clock signal applied to register R forming row address pointer RA, the time period in which each of row select signals Qr1-Qrn attains an H level corresponds to one period T. As to a clock signal applied to register R forming column address pointer CA, the time period in which each of column select signals Qc1-Qcm attains an H level corresponds to one period T. It is to be noted that an operation similar to the above-described operation is carried out even when the operation timing of column address pointer RA and column address pointer CA are interchanged.
The memory circuit shown in FIG. 30 will be described in detail with reference to FIG. 34.
Referring to FIG. 34, a memory circuit includes a write bit line WBL, a read bit line RBL, write and read word lines RWWL1-RWWL3, n channel MOS transistors Q111-Q117, and capacitors C111, C112.
Transistor Q111 is connected to write bit line WBL. Transistor Q111 has its gate connected to word line RWWL2. C111 is connected to transistor Q111 and a ground potential. Transistor Q112 has its gate connected to capacitor C111 and transistor Q111. Transistor Q112 is connected to ground potential and transistor Q113. Transistor Q113 is connected to read bit line RBL. Transistor Q113 has its gate connected to word line RWWL1. Read bit line RBL is connected to a predetermined precharge voltage V.sub.p via transistor Q117. Transistor Q117 has its gate supplied with a predetermined precharge signal PC.
According to the above-described structure, the data transmitted by write bit line WBL is stored in capacitor C112 via transistor Q111, whereby the potential of read bit line RBL is determined according to the charge of capacitor C111. Transistors Q111-Q116 and capacitor C112 are similar to transistors Q111-Q113 and capacitor C111.
The operation of the memory circuit of the above structure will be described hereinafter with reference to the timing chart of FIG. 35.
Referring to FIG. 35, the operation of the memory circuit at a timing L2 where word line WWL2 attains an H level will be described first. At the timing PC1 before word line WWL2 attains an H level, the potential of readout bit line RBL is precharged and maintained at the H level. When word line RWWL2 attains an H level at timing L2, transistors Q111 and Q116 forming the memory circuit are turned on. Here, the potential of write bit line WBL is stored and maintained in storage capacitor C111. When the potential of storage capacitor C112 attains an H level, transistor Q115 is turned on, whereby the potential of readout bit line RBL is pulled down to an L level through transistors Q115 and Q116. Similarly, when the potential of storage capacitor C112 attains an L level, transistor Q115 attains an OFF state, and the potential of readout bit line RBL remains at the H level. Therefore, the data stored in a memory circuit can be read out by sensing the two states with a sense amplifier (not shown).
In a general video signal processing, the SAM uses the memory capacity of one scan line (x words) of a video signal as one unit. When a memory capacity of y units is required, a row address pointer RA and a column address pointer CA corresponding to N rows and M columns as described above were used to allocate the memory cells of the capacity of y units into N rows and M columns to sequentially select the N rows and M columns similar to the case of an SAM of one unit. This means that the circuit complexity of the address pointer is increased as the memory capacity becomes greater, resulting in increase in the chip area and power consumption of the SAM.